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Cypress Semiconductor /psoc63 /FLASHC /FM_CTL /TM_CMPR[5]

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Interpret as TM_CMPR[5]

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DATA_COMP_RESULT)DATA_COMP_RESULT

Description

Do Not Use

Fields

DATA_COMP_RESULT

The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column ‘Column_Number’ is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. ‘0’: FALSE (not equal)

‘1’: TRUE (equal)

Links

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Register License

Copyright 2016-2018 Cypress Semiconductor Corporation \n Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at \n
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data